Power supplies having protection circuits

ABSTRACT

A power supply including an inverter receiving a DC input signal from a DC input source ( 11 ). The inverter is comprised of two half bridges (S 1 A, S 2 A and S 1 B, S 2 B). Each inverter is driven by a signal source ( 13 A,  13 B), which outputs an AC signal. The output from each inverter is input to a first stage harmonic filter. The power supply includes an output circuit that includes first and second rectifiers (D 1 , D 2 ) arranged about a point so that if the inverter attempts to drive the point beyond a predetermined first and second voltage, the respective rectifier conducts in order to return at least one of power and current to the DC input source. The output from the first harmonic filter (L 1 A, C 1 ; L 1 B, C 1 ) is output to a second harmonic filter (L 2 , C 2 ) and is then output from the power supply.

BACKGROUND

1. Technical Field

This invention relates generally to power supplies for supplyingalternating power and, more particularly, to a protection circuit forthe switching portion of a power supply.

2. Discussion

Radio frequency (RF) energy is used in various industries for thetreatment of materials through induction heating, dielectric heating,and plasma excitation. Plasma excitation can take the form of inductive,capacitive, or true electromagnetic (EM) wave, microwave, couplings.Generators which provide this RF energy utilize many circuit topologiesranging from single class A transistor amplifiers providing a few tensof watts to self-oscillating tube (valve) generators providing manythousands of watts.

The semiconductor manufacturing industry utilizes RF plasmas fordepositing and etching micron and sub-micron sized films. A typicalpower supply for this application may consist of a line frequencytransformer/rectifier/capacitor DC power supply and high frequency (HF)linear power amplifier. Typical power and frequency values may be up to10 KW within the range of 400 KHz to 60.0 MHz. The linear poweramplifier employs high frequency/very high frequency (HF/VHF) RF powertransistors having high power dissipation capability. Such a powersupply or generator would have power controllable to 1 or 2% precisionover a 100:1 output load range. Usually the generator is specificallyconfigured to output to a defined load, usually 50 ohms, but should beable to drive any load, even if mismatched, without failure. Typicalprotection schemes reduce the power. For example, the drive level to alinear amplifier is reduced to correspondingly reduce current or powerdissipation. In a 50 ohm system, variation from the typical 50 ohms canbe measured as reflected power. The drive level is reduced to limitreflected power.

FIG. 1 shows a typical transformer-coupled push-pull RF power amplifierhaving switches or transistors S1, S2 driven by sine waves which are outof phase. A five element harmonic rejection filter includes inductorsL1, L2 and capacitors C1, C2, and C4. The harmonic rejection filtertypically ensures a high purity or uniform sine wave output. No biasingschemes are shown which may be class AB or class B. Either bipolarjunction transistors (BJTs) or metal oxide semiconductor field effecttransistors (MOSFETs) are typically used. The transformer T1 has a ratiochosen to match the required power for a given DC supply voltage,usually 28V or 50V. Detailed circuitry follows standard industrypractice for broadband HF/VHF power amplifier design as would be usedfor communications.

The amplifier of FIG. 1 offers one primary advantage, but severaldisadvantages. The primary advantage is that a broadband design, theoutput frequency is easily changed simply by varying the drive or inputfrequency. For a given output frequency, only the output filter needs tobe changed. If the basic linearity/purity of the amplifier is goodenough, dispensed with altogether. The circuit of FIG. 1 has thedisadvantages of poor efficiency and high transistor power dissipation.Efficiency theoretically cannot exceed 70% but typically is no betterthan 50%. To address the high power dissipation, many applications useexpensive, special RF transistors which often employ beryllium oxide(BEo) low thermal resistance technology. This often requires large airor water cooled heatsinks. There is a large amount of data published onRF linear amplifier design. Any power supply manufacturer desiring todesign a generator can use the transistor manufacturer's applicationcircuit with a high degree of confidence.

As can be seen in FIG. 2, the circuit of FIG. 2 utilizes a differentmode of operation offering high efficiency and low power dissipation.The drive signals in the circuit of FIG. 2 are fixed at square waves sothat the transistors are now in a switching rather than a linear mode ofoperation. That is, the switches or transistors S1, S2 of FIG. 1 operatein a region between fully off and fully on. The switches or transistorsS1, S2 of FIG. 2 operate by switching from fully on to fully off. Theoutput of transformer T1 is now a square wave. A four element filterincluding inductors L1, L2 and capacitors C1, C2 filters out therequired fundamental frequencies to yield a sinusoidal output. CapacitorC4 is removed so that the filter provides an inductive input, in orderto reject harmonic current. Although the transistor and transformervoltages are square, the currents are sinusoidal. Efficiency can now be100%, and typically falls within the range of 80-95%. Such a circuit isusually referred to as a resonant converter or inverter rather than anamplifier.

The circuit of FIG. 2 suffers some disadvantages. The filter issufficiently selected for a particular output frequency so that only afixed or narrow frequency range or band of operation is possible. Also,the output power cannot be directly controlled. Unlike, FIG. 1, thecircuit of FIG. 2 cannot connect directly to a line or outlet voltage.Rather, the DC input to FIG. 2 requires regulation using an additionalpower converter, typically implemented using a switched mode converter.Further, mismatch loads can cause high circulating currents between thefilter and transistors. The circulating currents are not necessarilylimited by limiting the DC input current.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a power supply circuit having aDC input supplies alternating power to a load. An inverter generates analternating output, and an output circuit directly receives thealternating output and feeds it to a load. The output circuit includesfirst and second rectifiers connected relative to a point in the outputcircuit so that if the inverter attempts to drive the point to a voltagewhich exceeds either a predetermined positive voltage or a predeterminednegative voltage, a respective one of the first and second rectifiersconducts to cause voltage and/or current to return to the source of DCvoltage. The voltage and/or current is fed back into the inverter. Thismay be achieved, for example, by the first rectifier being connectedbetween the ground or negative input of the DC input and the point andthe second rectifier being connected between the point and the positiveinput of the DC voltage. It will be appreciated that when eitherrectifier conducts it clamps the point to the voltage of its associatedrespective input of the DC input. The rectifiers may be embodied asdiodes.

In an alternative arrangement, the rectifiers may be connected to aseparate voltage source or sources, and the clamping will occur to thevoltages determined by the source or sources. The present inventionincludes a constant voltage sink if, for example, the first and secondrectifiers are implemented using Zener diodes. The Zener diodes maydissipate at least some of the voltage and/or current, and they may havean associated transistor through which a higher level of energy can bedissipated. In either case the dissipation occurs through heating. TheZener diodes may be connected back to back so that each diode performsthe rectifying action for the other diode. Alternatively, a suitable,separate rectified diode, or rectifying circuit, is used in series witheach Zener. In the construction in which the first and second diodes areconnected on either side of the point, each diode may be implemented byforming a chain of diodes, such as Shottky diodes, and the diodes may beconfigured in a single ceramic substrate.

The inverter may include at least two switching devices. The powersupply circuit may also include an inductance connected to a pointbetween the two switching devices so that the charging and dischargingof the devices, and any associated capacitance, is substantially bymeans of the inductive current.

In yet another embodiment of the present invention, a power supplycircuit has a DC input and supplies alternating power to a load. Aninverter generates an alternating output, and an output circuit directlyreceives the alternating output and feeds it to a load. The outputcircuit further includes a constant voltage sink for dissipating voltageand/or current if the inverter seeks to drive a predetermined point inthe circuit to a voltage which lies outside a predetermined voltageband.

In yet another aspect of the present invention, a power supply includesa supply output and first and second power supply circuits as definedabove. The output of each first and second power circuit is connected inparallel to the supply output. Respective alternating signal sourcesswitch the inverters of the first and second supply circuits and controla circuit for altering the relative phase of the signal sources toadjust the power at the supply output. The power supply circuits may beconnected in series or parallel.

In yet another aspect of the present invention, a power supply suppliesalternating current to a load. First and second power supply circuitseach include inverters. An alternating signal source supplies analternating signal to switch the inverter and to respective poweroutputs. The power outputs are connected in parallel or series to thesupply output through harmonic filters. A control circuit varies therelative phase of the alternating signals to adjust the power at thesupply output.

In yet another aspect of the present invention, an input circuit for avoltage inverter has at least two switching devices. The circuitincludes an inductance connected to a point between the devices so thatcharging and discharging the devices, and any associated capacitance, issubstantially through an inductive current.

For a more complete understanding of the invention, its objects andadvantages, reference should be made to the following specification andto the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be performed in a number of ways and specific relatedinventions will now be described, by way of example, with reference tothe accompanying drawings, in which;

FIGS. 1 and 2 are circuit topologies practiced in the prior art, asdescribed above;

FIG. 3 is a power supply circuit arranged in accordance with theprinciples of the present invention;

FIG. 4 illustrates a related invention in which circuits are connectedin series to produce a combined output;

FIG. 5 is a related invention in which circuits are connected inparallel to produce a combined power output;

FIG. 6 is a related invention in which each half of a switching bridgeis protected by a single clamping diode pair;

FIG. 7 is a related invention in which is a resonant circuit and singleswitch provide an output and in which a single diode clamping pairprotects the circuit;

FIG. 8 is a three level implementation of the circuit of FIG. 7;

FIG. 9 is a related invention showing a half bridge inverter and aprotection circuit;

FIGS. 10-12 illustrate alternative configurations for switching devices,depending upon the particular switching device;

FIG. 13 is a circuit having a capacitor in parallel with one of theclamping diodes;

FIG. 14 is a circuit having a capacitor in parallel with each of theclamping diodes;

FIG. 15 is a circuit having a voltage divided across a series ofcapacitors and diodes;

FIG. 16 is a circuit showing an inductance and RC circuit in theprotection circuit;

FIG. 17 shows a MOSFET circuit for improving operation of the filternetwork;

FIG. 18 is a circuit for an alternative input circuit for an inverterfor addressing device capacitance;

FIG. 19 shows an inverter circuit for addressing device capacitanceimplemented using multiple FETs;

FIG. 20 is an improvement to the input circuit of FIG. 18;

FIG. 21 shows an inverter having an additional LC series circuit;

FIG. 22 illustrates a power supply circuit for varying the clampingvoltage;

FIGS. 23-26 illustrate alternative constant voltage sink arrangementsfor use with the inverter of FIG. 22.

FIGS. 27a-27 m illustrate waveforms taken from an exemplary half bridgeinverter incorporating a protection circuit;

FIGS. 28a-28 f illustrate comparative waveforms from an exemplary halfbridge inverter not incorporating a protection circuit;

FIG. 29 is a block diagram of a control circuit for a power supply;

FIG. 30 is a block diagram for a plasma system utilizing a protectioncircuit.

FIG. 31 is a matching network for the control circuit of FIG. 30.

DETAILED DESCRIPTION OF THE INVENTION

With reference to FIG. 3, a voltage inverter circuit is generallyindicated at 10 and has a direct current (DC) voltage source input at 11and an alternating current (AC) output at 12. It should be noted fromthe outset that in describing the figures, switches will generally bereferred to using S followed by a number; capacitors will be referred tousing C followed by a number; inductors will be referred to using Lfollowed by a number; diodes will be referred to using D followed by anumber; and transformers will be referred to using T followed by anumber. Further, in circuits which have a generally symmetric topology,each of the above reference symbols may be followed by a letter suffixto indicate generally similar, symmetric elements.

Switches S1, S2 receive as input respective out of phase square wavesignals from a signal source or generator 13. The square wave signalsturn on switches S1, S2 in a manner to reverse the polarity of thevoltage across inductor whenever either L1 switch S1 or S2 is turned on.When signal source 13 drives switches S1, S2 in such a manner, switchesS1, S2 and capacitor C3 cooperate to invert the DC input signal to an ACsignal which is applied to inductor L1. This creates the alternatingoutput at 12, with DC components being blocked by capacitor C4. Thefrequency of the output signal at 12 depends upon the frequency of thesignals output by signal source 13. A four element harmonic filtercomprising inductors L1, L2 and capacitors C1, C2 operate generally asdescribed above. Inductor L1 and capacitor C1 form a first stage of theharmonic filter and inductor L2 and capacitor C2 form a second stage ofthe harmonic filter. The output filter removes harmonic components ofthe signal input to inductor L1 to improve the purity of the output signwave and matches the required output power for a given input voltage tothe output impedance, which is typically 50 ohms.

As discussed above, the circuit of FIGS. 1 and 2 could be highlyvulnerable to high circulating currents created by mismatch loads. Apair of clamping diodes or rectifiers D1 and D2 inserted between thefirst and second stage harmonic filters alleviates potential damage dueto circulating currents. Diode D2 extends from the negative rail of DCinput source 11 up to a node X. Diode D1 extends from node X to thepositive rail of DC input source 11. In operation, if the circuitattempts to drive the node X beyond the rail voltage, in one directionor the other, then the diode associated with that rail will turn on andbecome conductive. When the diode turns on, the diode clamps node X tothe rail voltage and feeds back the excess voltage and/or current intothe inverter, particularly input source 11 and capacitor C3. Moreparticularly, if the circuit attempts to drive node X above the voltageat the positive rail of the DC input 11, diode D1 turns on providing acurrent path including the body diode of switch S2 back to the DC inputvoltage source 11 and capacitor C3. Similarly, if the circuit attemptsto drive node X below the negative rail of DC source 11, diode D2becomes conductive, providing a current path back including the bodydiode of switch S1 to DC input source 11 and capacitor C3. As theeffects of mismatch loads increase with frequency, the circuit of FIG. 3enables an inverter to be used at frequencies which were previouslydifficult to achieve.

FIG. 4 illustrates a related invention in which the output of two powersupply circuits are placed in series. FIG. 4 includes two halves A and Barranged in a full-bridge configuration. The circuit of FIG. 4 enablesadjustment of power at output 12 by varying the phase between theswitching signals applied to each of the two halves A and B.

A first half of FIG. 4 includes a pair of switches S1A, S2A whichreceive a pair of AC signals output by signal source 13A. Switches S1A,S2A are connected in series between the negative and positive voltagerails of a DC power source 11. The output from switches S1A, S2A isapplied to inductor L1A, which forms a two stage, four element harmonicfilter in combination with inductor L2A and capacitors C1A, C2A. A firstclamping diode D1A has a negative terminal or cathode connected to thepositive rail of DC input source 11 and a positive terminal or anodeconnected between inductors L1A, L2A. A second clamping diode D2A has apositive terminal or anode connected to the negative terminal of DCsource 11 and a negative terminal or cathode connected to the positiveterminal of clamping diode D1A. The output from the harmonic filter isconnected to a first end tap of transformer T1.

Clamping diodes D1A, D2A provide protection to the left half of thecircuit of FIG. 4. When the circuit attempts to drive the voltage atnode XA above the positive rail of DC source 11, diode D1A becomesconductive, thereby clamping the voltage at node XA to approximately thepositive rail voltage of DC input source 11, and providing a path backto DC input source 11 and capacitor C3. Similarly, when the circuitattempts to drive node XA below the negative rail voltage of DC inputsource 11, diode D2A turns on, clamping the voltage at node XA toapproximately the negative rail voltage of DC input source 11 andprovides a circuit path back to DC input source 11 and capacitor C3,thereby protecting the left half of the circuit of FIG. 4.

The circuit of FIG. 4 also includes a second half, half B, whichincludes switches S1B, S2B. A signal source 13B outputs a pair of ACsignals to switches S1B, S2B. It should be noted that signal sources13A, 13B may be combined into a single unit. Half B also includes a fourelement, two stage harmonic filter comprising inductors L1B, L2B andcapacitors C1B, C2B. Half B also includes a pair of clamping diodes D1B,D2B arranged in half B as described in half A. The output from circuithalf B is connected to an end tap of transformer T1. Circuit half Boperates as described with respect to circuit half A. Transformer T1provides isolation between circuit halves A and B and the output 12.Circuit halves A and B are connected in series through the input coil oftransformer T1.

Circuit halves A, B are combined in series such that altering the phasebetween the switching signals controlling each half varies the power atoutput 12. In particular, when switch S1A and switch S1B are actuatedand deactuated at the same times, switches S1A, S1B are said to operatein phase or at 0 degrees phase. Conversely, if switch S1A is offwhenever switch S1B is on and switch S1A is on whenever switch S1B isoff, the switches are said to be out of phase or at 180 degrees phase.Similar terminology applies to each of switches S2A, S2B. The phasebetween each circuit half A, B is determined by a phase controller 14which provides an output signal to each of signal sources 13A, 13B inorder to vary the relative phases between each circuit half. Maximumpower at output 12 results when circuit halves A and B are operated at180 degrees phase or out of phase. Minimum power at output 12 resultswhen circuit halves A and B are operated at 0 degrees phase or in phase.When the phase is zero, each half sees an open circuit regardless of theload impedance. Transformer T1 combines the outputs effectively inseries, and no blocking capacitors are required before output 12. Thecircuit components forming the harmonic filter in each circuit half Aand B must be matched or equal to ensure zero output at 0 degrees phase.For example, the values for L1A, L2A, C1A, and C2A should be equal thevalues for L1B, L2B, C1B, and C2B.

FIG. 5 depicts a related invention in which a first circuit half A and asecond circuit half B are combined in parallel. Circuit half A includesa pair of switches S1A, S2A which receive respective AC input signalsfrom signal generator 13A, which may be combined with signal source 13Bto form a single unit. Switches S1A, S2A are connected in series betweenthe respective positive and negative rails of DC input source 11. Theoutput from switches S1A, S2A is applied to a four element, two stageharmonic filter comprising inductors L1A, L2A and capacitors C1A, C2A.

A pair of clamping diodes D1A, D2A are arranged in series between therespective positive and negative rails of DC input source 11. Thenegative terminal or cathode of diode D1A connects to the positive railof DC source, and the positive terminal or anode of diode D1A connectsto node XA. The negative terminal or cathode of diode D2A connects tonode XA, and the positive terminal or anode of diode D2A connects to thenegative rail of DC power source 11. The output from circuit half A isdetermined in accordance with the voltage between the negative rail ofDC input source 11 and the output from the four element filter. Theoutput from the filter is applied to a blocking capacitor C4, whichblocks any DC component of the output signal. Capacitor C4 also connectsto the output 12. In operation, clamping diodes D1A, D2A protect thecircuit elements of circuit half A by providing a circuit path to DCinput source 11 and capacitor C3 when the circuit attempts to drive nodeXA beyond a predetermined threshold defined by each of the respectivenegative and positive rails of DC source 11.

Circuit half B is similarly arranged to and operates in the same manneras circuit half A. In a parallel connection of circuit halves A, B, asshown in FIG. 5, varying the phase of operation between each respectivehalf A, B varies the power at output 12. In particular, when switchhalves A, B are operated at 0 degrees or in phase, maximum power isgenerated at output 12. Conversely, when the switch halves A, B areoperated at 180 degrees or out of phase, a short circuit appears, and aminimum power appears at output 12. A phase controller 14 provides acontrol signal to each of signal generators 13A, 13B in order to controlthe relative phases between each circuit half A, B. With the phase at180 degrees each circuit half now sees a short circuit regardless ofload impedance. Note that because capacitors C2A and C2B are inparallel, they can be combined into a single component. The circuitcomponents forming the harmonic filter in each circuit half A and B mustbe matched or equal to ensure zero output at 180 degrees phase. Forexample, the valves for L1A, L2A, C1A, and C2A should be equal thevalues for L1B, L2B, C1B, and C2B.

FIG. 6 depicts a circuit having circuit halves A, B which cooperate toapply signals to common elements prior to output 12. Circuit half Aincludes a pair of switches S1A, S2A arranged in parallel between therespective positive and negative voltage rails of DC input source 11.The output from switches S1A, S2A are input to an inductor L1A. A signalsource or generator 13A outputs AC signals which control actuation ofswitches S1A, S2B. Circuit half B includes a pair of switches S1B, S2Barranged in series between the respective positive and negative voltagerails of DC input source 11. The output from switches S1B, S2B are inputto inductor L1B. A signal source or generator 13B, which may be combinedwith signal source 13A into a single unit, provides AC signals tocontrol actuation and deactuation of each respective switch S1B, S2B.

A pair of clamping diodes D1, D2 are arranged in parallel with therespective switch pairs S1A, S2A and S1B, S2B. Clamping diodes D1, D2provide a circuit path back to DC input source 11 and capacitor C3 wheneither circuit half A, B attempts to drive node XY beyond apredetermined voltage defined by the respective positive and negativerails of DC input source 11.

Capacitor C1 is arranged between the negative voltage rail of DC source11 and node XY. The voltage between the negative rail of DC source 11and node XY defines an input voltage to a filter defined by inductor L2and capacitor C2, which forms a second stage of the harmonic filterformed by inductors L1A, L2B, L2 and capacitors C1, C2. Capacitor C1cooperates with each of respective inductors L1A, L2B to provide a firststage of harmonic filter. A blocking capacitor C4 removes DC componentsof the signal prior to output at output 12.

Clamping diodes D1, D2 provide a circuit path back to DC input source 11and capacitor C3 when either circuit half A, B attempts to drive node XYabove the positive voltage rail of DC source 11 or below the negativevoltage rail of DC source 11. Thus, regardless of what circuit half A, Bdrives node XY beyond the above-described predetermined thresholds,clamping diodes D1, D2 operate to protect the circuit of FIG. 6 byproviding a circuit path back to DC source 11 and capacitor C3.

The circuit of FIG. 6 also includes a phase controller 14 forcontrolling the relative phases between circuit halves A, B bygenerating control signals to each of respective signal sources 13A,13B. In FIG. 6, maximum power is provided at output 12 when switchhalves A, B operate in phase or at zero degrees phase, and minimum poweris provided at output 12 when circuit halves A, B operate out of phaseor at 180 degrees phase. In the circuit of FIG. 6, inductors L1A and L1Bmust be matched to ensure zero output at 180 degrees phase.

FIG. 7 depicts a circuit having circuit halves A, B which are combinedin parallel to provide an AC signal at output 12. With reference tocircuit half A, switch S1A receives an AC signal from signal source 13A.Switch S1A is placed in series with a commutating inductor L3A betweenthe respective negative and positive voltage rails of DC power source11. A capacitor C6A is placed in parallel with switch S1A. Commutatinginductor L3A and capacitor C6A cooperate to form a tank circuit so thatcircuit half A provides a single-ended inverter function. The tankcircuit outputs a half-rectified sine waveform. A blocking capacitor C7Aremoves DC components from the signal output from switch S1A andcommutating inductor L3A. Capacitor C7A couples the AC together andensures the same AC voltage across each device, as will be seen in FIG.8. Note that L3A and L3B can be cross coupled to promote equal sharing.The ratio inductors L3A to L1A determines the variation of stress ofswitch S1A. If the current through inductor L3A is relatively largecompared to that through inductor L1A then the variation due to the loadthrough inductor L1A will have a limited effect on the stress on switchS1A. The circuit of FIG. 7 has the disadvantage that even harmonics aregenerated and the DC voltage across C7A has some dependence on the load.This means a transient charging current may flow under some loadchanges. Output from blocking capacitor C7A is input to inductor L1A.

Second switch half B includes a switch S1B driven by an AC signal outputby signal source 13B. Switch S1B is in series with commutating inductorL3B between the respective negative and positive rails of DC inputsource 11. A capacitor C6B is placed in parallel with switch S1B.Commutating inductor L3B and capacitor C6B form a tank circuit. Theoutput from switch S1B and inductor L3B is applied to blocking capacitorC7B, which removes DC components from the signal. Inductor L1B connectsto capacitor C7B.

Inductors L1A and L1B interconnect at node XZ and provide an output toinductor L2 and capacitor C2. The other terminal capacitor C2 isconnected to the negative rail of DC voltage source 11. A capacitor C1is connected between the negative rail of DC voltage source 11 and nodeXZ. Accordingly, inductors L1A, L2 and capacitors C1, C2 from atwo-stage harmonic filter for the output from circuit half A. Similarly,inductors L1B, L2 and capacitors C1, C2 form a two-stage harmonic filterfor the output from circuit half B. Blocking capacitor C4 removes DCcomponents from the signal provided at output 12.

FIG. 7 also includes a pair of clamping diodes D1, D2 arranged in seriesbetween the respective positive and negative rails of voltage source 11.The negative terminal or cathode of diode D1 connects to the positiverail of DC source 11, and the positive terminal or cathode of diode D1connects to node XZ. The negative terminal or cathode of diode D2connects to node XZ, and the positive terminal or anode of diode D2connects to the negative rail of DC source 11.

When either circuit half A, B attempts to drive the voltage at node XZabove a predetermined threshold, one of clamping diodes D1, D2 turns on,thereby providing a circuit path from node XZ back to DC source 11 andcapacitor C3. For example, when the circuit of FIG. 7 attempts to drivenode XZ to a voltage above the positive rail of DC source 11, diode D1becomes conductive, thereby providing a circuit path for excess voltageand current back to DC input source 11 and capacitor C3. Similarly, whenthe circuit attempts to drive the voltage at node XZ below the voltageat the negative rail of DC input source 11, diode D2 becomes conductive,providing a circuit path back to DC input source 11 and capacitor C3.

The circuit halves A, B of FIG. 7 are arranged in a parallelconfiguration. When the relative phase of the control signalscontrolling switch S1A and switch S1B is in phase, or at 0 degrees,output 12 receives maximum power. Conversely, when the phase between thesignals driving switch S1A and S1B are out of phase, or at 180 degrees,output 12 receives a minimum power. A phase controller 14 varies therelative phase between circuit halves A, B by providing an input tosignal to each of signal sources 13A, 13B. The circuit componentsforming the harmonic filter in each circuit half A and B must be matchedor equal to ensure 180 degree output phase. For example, L1A, L2A, CIA,and C2B should equal the values for L1B, L2B, C1B, and C2B.

A particular benefit of the circuit of FIG. 7 is that during operationat high frequencies, driving switches alternately within a same circuitpath generally becomes more difficult. By utilizing a tank circuitformed by inductor L3 and associated capacitor C6, less precision isgenerally required of the switching on a particular circuit half.

FIG. 8 depicts a three level implementation of the single-ended invertercircuit of FIG. 8. FIG. 8 includes a pair of circuit halves A, B, whereeach pair includes three levels designated by prime (′), double prime(″), and triple prime (′″). With reference to circuit half A, each levelincludes a switch S1A which receives an AC signal from signal source13A. Switch S1A connects to an inductor L3A and is placed in parallelwith the capacitor C6A. Inductor L3A and capacitor C6A cooperate to forma tank circuit. The output from inductor L3A and switch S1A is input toblocking capacitor C7A, which removes DC components from the output ofconductor L3A and switch S1A. A capacitor C5A is placed in parallel withthe series connection of switch S1A and inductor L3A. Each switch S1A′,S1A″, S1A′″ receives analog signal from signal source 13A.

Capacitors C5A′, C5A″ C5A′″ decouple the three levels. Each capacitorC5A′, C5A″, C5A′″ passes current and blocks AC, thus providing a currentloop for each DC portion of each stage. Capacitors C7A′, C7A″, C7A′″ ACcouple the outputs of each level together and have impedances which arenegligible at the frequency of interest. Accordingly, each level has avoltage which is approximately equal. For example, if the voltage outputby DC input source 11 is 300 volts, the voltage across each capacitor is100 volts. Thus, each level of circuit half A must handle only ⅓ of thevoltage output by DC source.

Similarly, circuit half B includes three levels, with each level havinga switch S1B connected in series with an inductor L3B. Switch S1B isalso connected in parallel with a capacitor C6B which forms a tankcircuit with inductor L3B, as discussed above. A blocking capacitor C7Bremoves DC components from the output of inductor L3B and switch S1B.Each level is also connected in parallel with a capacitor C5B. Theelements operate as described above with respect to circuit half A. Eachswitch S1B′, S2B″, S3B′″ receives an AC signal from a signal generator13B.

The output from the three levels of circuit half A is combined and inputto inductor L1A. Inductor L1A cooperates to form a two-stage harmonicfilter with inductor L2 and capacitors C1, C2 to remove harmoniccomponents output from circuit half A. Similarly, the output from eachlevel of circuit half B is combined and input to inductor L1B which alsocooperates with inductor L2 and capacitors C1, C2 to form a two stageharmonic filter which removes harmonic components from the AC signaloutput from circuit half B. A blocking capacitor C4 is connected at theoutput of the harmonic filter to remove DC components in the signalprovided to output 12.

FIG. 8 also includes a pair of clamping diodes D1, D2 arranged in seriesbetween the respective positive and negative voltage rails of DC inputsource 11. Clamping diodes D1, D2 cooperate to provide a circuit pathback to DC source 11 and capacitor C3 when either circuit half attemptsto drive node XZ beyond a predetermined threshold defined by therespective negative and positive rails of DC input source 11. Inoperation, when either circuit half attempts to drive node XZ to avoltage greater than the positive rail of DC input source 11, diode D1turns on, creating a circuit path back to DC input source 11 andcapacitor C3. Similarly, when either circuit half A, B attempts to drivethe voltage at node XZ below the negative rail of DC input source 11,diode D2 turns on, creating a circuit path back to DC input source 11and capacitor C3.

In operation, the relative phase between circuit halves A, B determinesthe power provided to output 12. When the relative phase between circuithalves A, B is 0 degrees or in phase, output 12 receives a maximumpower. Conversely, when the relative phase between the AC signalsdriving the switches for the respective circuit halves A, B is 180degrees, or out of phase, output 12 receives a minimum power.

A particular advantage of the circuit of FIG. 8 is that by placing threecircuits in series between the respective negative and positive rails ofvoltage source 11, each level handles only one-third of the overallvoltage across the respective negative and positive rails of DC source11. This enables utilization of 400-500 volt devices for power supplieshaving DC input of approximately 300 volts, as only one-third of theinput voltage is handled by each level, rather than the entirety of thevoltage in a single level implementation. Such 400-500 volt devices arewidely available and provide optimum characteristics for a 300 voltinput system.

FIG. 9 shows a circuit diagram for an inverter having a protectioncircuit. A DC voltage of 300 volts is applied across the voltage railsof the circuit of FIG. 9. A first capacitor C3-1 is embodied as a 2.2microfarad (μF) capacitor having a 400 volt (V) capacity and a secondcapacitor C3-2 is embodied as a 220 μF capacitor having a 380V capacityare placed in parallel between the voltage rails. A first AC signal isapplied by a signal source (not shown) to the terminals of an isolationtransformer T3. A second AC signal from the signal source (not shown) isapplied to the input of a transformer T4.

The output from transformer T3 is input to a pair of switches S1-1, S1-2through a 22 ohm (Ω) resistor. Similarly, the output from transformer T4is input to a second switch pair S2-1, S2-2 through a 22 ohm (Ω)resistor. The switches are selected from an IRF740 package. The switchpair S1-1 and S1-2 are placed in parallel, as is the switch pair S2-1and S2-2. Such parallel arrangement of the dual switches of a singleswitch pair reduces the current handling requirement of each switch. Theoutput from the switch pairs S1, S2 is input to a 10.3 microhenry (μH)inductor L1 which cooperates with a 13.2 μH inductor L2 and a 30nanofarad (ηF) capacitor C1 and a 10 ηF capacitor C2 to provide a fourelement harmonic filter for removing harmonics from the output ofswitches S1, S2. Blocking capacitor C4 is embodied as a 2.2 μF capacitorhaving a 400V capacity.

Clamping diodes D1 and D2 are arranged in series between the respectivepositive and negative rails of voltage of DC source 11. Clamping diodesD1, D2 are preferably selected from a package HFAT660.

The circuits described above typically operate over a limited range offrequency. Because the LC networks are generally low pass filters,maximum power throughput varies inversely with frequency. Also, as thefrequency decreases, distortion from the harmonics will start to appear.Satisfactory operation over at least a 30% bandwidth has been observed.

Other circuits exist having a voltage source inverter feeding a multipleLC network where clamp diodes may be connected between the network andDC voltage source. While half bridge inverter circuits are illustrated,it should be understood that full bridge and single ended inverters arealso included. The LC network values and clamp point are preferably, asdescribed herein, advantageously selected so that excessive circulatingenergy can be returned to the supply, preventing the build-up ofexcessive current and voltage, thereby protecting the components. Inaddition such a selection may ensure that the current always looksinductive at the source inverter, addressing diode recoveryconsiderations. Transformers may be included in such a network to helpmatch the output, clamp point, and inverter transistors or to provideisolation.

Further, two voltage source inverters may be connected to a networkdescribed herein so that the power level may be controlled by the phaserelationship. In addition to the phase relationships described herein,non-symmetrical networks will lead to more complex phase relationships.Symmetrical networks offer the advantage that maximum and minimum powerphases will not depend on frequency.

The above phase modulation circuits of the type described herein raisethree potential design considerations.

First, under certain, limited conditions, DC power circulates from onebridge side to the other. When this occurs, although the FETs still seeinductive turn off, when averaged over the whole cycle, the FETs are netrectifying. That is, more charge flows through the FET in a reverserather than a forward direction. Consequently, if the current is highenough in reverse to turn on the body diode, the body diode will not befully recovered when the transistor turns off, resulting in high powerdissipation. This effect will be exaggerated by the negative temperaturecoefficient of the body diode voltage drop as the device heats up,potentially leading to thermal runaway.

This first consideration can be addressed at low frequencies byaccepting the loss or by using reverse isolation diodes. At higherfrequencies, the FETs should be selected to have sufficiently lowresistance so that reverse current is always handled by the channel.This is easier to accomplish with low voltage devices because the onresistance is proportional to the voltage raised to the 2.5 ^(th) power,while the diode drop is independent of voltage.

Second, a high gain condition exists when the LC networks becomeresonant at low phase and are not clamped until the amplitude, and thusthe forward power, of the output is relatively high. This condition willnot likely harm the devices, but will affect the accuracy of control.

This second consideration can be addressed by utilizing very precise andstable phase controller or modulator design or by inserting resistors inthe output network which will lower the Q and broaden the phasecharacteristic. Utilizing resistors that require just 1 or 2% of the 50ohm power appears sufficient. This consideration only appears when thereis no real power consumed at the load, such as may occur during theslightly artificial conditions of the load being purely reactive.Generally a plasma chamber, cable, and matching network will lower the Qsufficiently.

Third, the phase to power control characteristic may exhibit inflectionsor variations under various poor match conditions. For example, as thephase varies smoothly from zero to a maximum, the power increases fromzero, decreases slightly, then continues to increase. This may causeoscillation in conjunction with the non-linear plasma impedance/powerfunction.

This consideration is theoretical in its nature and may not be apractical consideration. The control algorithm may simply jump throughthe inflection, which typically disappears at matches better than 3:1voltage standing wave ratio (VSWR). Also, the power controlcharacteristic is inflection free for at least half of an infinite VSWRcircle, so the load can be placed somewhere on the VSWR circle usingcable length, pie networks, and the like. In practice, the circuit ofFIG. 6 is superior to FIG. 4 in that the inflections are less pronouncedand occur near maximum power which typically may not be reached inpractice.

The circuits described herein utilize metal oxide semiconductor fieldeffect transistors (MOSFETs). Although, MOSFETs are generally superiorto bipolar junction transistors (BJTs) or insulated gage bipolartransistors (IGBTs) at the frequencies of likely interest greater than 1megahertz (MHz).

FIGS. 10-12 depict configurations for implementing switches in thecircuits above using one of a MOSFET, BJT, or IGBT transistor. FIG. 10shows a MOSFET as used in the circuits described above. The MOSFETincludes a blocking diode which is inherent in the design of the MOSFET.FIG. 11, shows a BJT 20 and an anti-parallel diode 22. In the circuitsdescribed above, when implementing the switches using a BJT 20, ananti-parallel diode 22 must be included in order to provide a circuitpath when the clamping diodes D1, D2 are active.

Similarly, FIG. 12 shows a preferred configuration when implementing theswitches of the present invention utilizing an IGBT. FIG. 12 shows anIGBT 24 and an anti-parallel diode 26, which provides a similar functionas anti-parallel diode 22 of FIG. 11. It should be noted that otherswitching devices or circuit combination providing a suitable switchingand circuit path functions may also be used in the place of MOSFETswithout altering the principles of the invention.

FIGS. 13-15 depict alternative diode clamping circuits described withrespect to D1, D2. FIG. 13 depicts a diode clamping circuit includingdiodes D1, D2 and capacitor C1. This circuit has been described above.FIGS. 14 and 15 show implementations using alternate configurations ofthe diodes D1, D2 and capacitor C1. In each circuit, capacitor C1 may beimplemented utilizing two identical capacitors of half the value placedacross each diode, as shown in FIG. 14. Capacitors C1/2 are effectivelyin parallel, coupled through decoupling capacitor C3 (not shown in FIG.14). Decoupling capacitor C3 is made large relative to the operatingfrequency so its impedance is negligible, thereby assisting the circuitphysical layout and component power sharing.

As shown in FIG. 15, at higher frequencies it may be advantageous to usetwo diodes in series for each diode D1, D2. Generally lower voltagediodes have lower reverse recovery charge. With two diodes in series,the same charge flows through each diode. Dividing C1 up across eachdiode ensures equal sharing of the AC voltage.

As shown in FIG. 16, in a further variation of the clamping circuit,inductor L6 is placed in series with L1 and between the junction of theclamp diodes D1, D2 and filter capacitor C1. Inductor L6 is preferablyof a small value. This can soften the diode turn on and off, increasingthe efficiency of rectification. A snubber circuit formed by capacitorC7 and resistor R1 may be required to dampen high frequency ringing whendiodes D1, D2 turn off. Correctly chosen, this will also contribute toreducing high Q situations if the LC network becomes resonant at lowpower output, such as where there is a low phase angle between the twoparallel bridge circuits.

As discussed above, power control precision can be compromised as aresult of a high gain condition existing if the LC filter networksbecome resonant at low phase and are not clamped until the amplitude,and thus the forward power, of the phase is increased. This can beaddressed by a very precise and stable phase modulator design or byresistors connected in the output network and having a value sufficientto reduce the Q and broaden the phase characteristic. Consumingapproximately 1-2% of the 50 ohm power appears sufficient to addressthis consideration. This typically only occurs where low power isconsumed at the load, such as under the somewhat artificial condition ofpure reactive loads in test conditions. In practice, cable, matchingnetworks, and the load will sufficiently lower the Q. At larger phaseshifts the clamping diodes prevent the resonance.

Alternatively, the Q may be selectively lowered by switching inresistors at the clamp point only when the phase is low. This may beachieved using a comparator on the phase modulator demand, set to comeon for low values. This can then drive a relay, which may take the formof a MOSFET switch which is actuated when the phase difference isrelatively low, such as in low power demand. FIG. 17 shows a circuit forselectively inserting resistors at the clamp point. As shown in FIG. 17,a MOSFET SR can be advantageously used because the voltage swing islimited by the clamp diodes and because a MOSFET will conduct in bothdirections. Bias resistors R3, R4 can center the voltage swing withinthe range of SR. R2 is chosen to provide sufficient damping, and C8blocks DC from flowing through R2 and through the MOSFET SR. The inputto SR typically is provided through a control circuit. The output fromC8 is connected to the interconnection of diodes D1, D2.

As the operating frequency is increased the capacitance of FETstypically implementing the switches has a more significant effect oncircuit operation. FIG. 18 shows an enhancement to a half bridgecircuit.

In FIG. 18, capacitors C5 have been placed in parallel with capacitor C3(not shown). An inductor L3 is inserted between the inter connectionbetween capacitors C5 and the output of switches S1, S2. Inductor L3ensures that sufficient inductive current always flows to charge anddischarge the output and Miller capacitance of FETs S1, S2. Inductor L3also ensures that the current appears inductive if the output and clampnetwork allows capacitive load current to flow.

As discussed above, DC power may circulate from one bridge side to theother under certain conditions. As a result, while the FETs S1, S2 stillsee inductive turn off, when averaged over a whole cycle, the FETs S1,S2 are net rectifying. That is, more charge flows in a reverse ratherthan a forward direction. Consequently, if the current is high enough toreverse and turn on the body diode contained within the FET, the FETswitch will not be fully recovered when the transistor of the FET turnsoff, and high power dissipation will result. This will be exaggerated bythe negative temperature coefficient of the body diode voltage drop asthe FET device heats up, potentially leading to thermal run away.

As also discussed above, at low frequencies this condition can beaddressed by accepting the loss, or using reverse isolation diodes. Athigher frequencies the FETs should be selected to have sufficiently lowenough on resistance so that the reverse current is always handled bythe FET channel. This is easier to accomplish with low voltage devicesbecause the on resistance is proportional to the voltage raised to the2.5th power while diode drop is independent of voltage.

As shown in FIG. 19, two lower voltage FETs S1-1, S1-2 and S2-1, S2-2may be connected in series. These FETs will typically have one quarterof the on resistance compared to two FET devices in parallel and willdrop half the voltage through each. Thus, the threshold current fordiode construction will double. In FIG. 19, capacitors C6 may be placedin parallel with each switch S1-1, S1-2, S2-1, S2-2. Capacitors C6 maybe required to ensure equal voltage sharing, but also add to theeffective device capacitance. A capacitor C7 further promotes equalvoltage sharing and only passes imbalance currents. In thisconfiguration, fast recovery epitaxial diode (FREDFET) switches mayoffer advantages due to their reduced reverse recovery charge.

FIG. 20 shows yet another improvement to the circuit of FIG. 18. Twoclamp diodes DI1, DI2 are inserted in parallel with each of capacitorsC5. Diodes DI1, DI2 are selected to rectify current or voltage at thejunction for return to the supply. This cycles inductive current as inFIG. 18 to commutate the capacitance of the FETs S1, S2 and also absorbsDC from the FETs S1, S2 and returns the DC to the supply rails. This canalso handle any DC flowing from one bridge side to the other and thusalso address FET body diode recovery considerations. Capacitors C5 anddiodes DI1, DI2 may be configured in series and parallel combinationssimilarly to the main clamping arrangement, but typically require lowerpower handling capability. If a variable frequency of operation isdesired the circuit FIG. 20 offers the additional advantage that theturn-off current remains approximately the same, independent offrequency, so long as L3 and C5 have been chosen so that diodes DI1, DI2are always conducting.

An improvement to the circuit of FIG. 20 is shown in FIG. 21, whichincludes an additional LC series circuit including inductor LS andcapacitor CS. By properly selecting the values of inductor LS andcapacitor C5 so that the resonant frequency is between the primaryfrequency of the power supply and its third harmonic, the currentthrough inductor L3 increases with frequency and maintains the DCcurrent approximately constant.

Although negative and positive rails provide convenient referencevoltages for clamping a predetermined point which is responsive tomismatch effects and also allows feeding back of the voltage and/orcurrent to the inverter, it is also possible to connect the clampingdiodes across some other, predetermined voltage source so that clampingoccurs. Because the circuit must sometimes dissipate excess voltage andcurrent, referencing an alternate voltage source preferably includereferencing constant voltage sink.

FIG. 22 illustrates a circuit referencing voltages other than thenegative and positive voltage rails. A blocking capacitor C4 is insertedbetween the inductor L1 and the inverter switches S1, S2 so that Zenerdiodes Z1, Z2 set respective high and low voltage references forclamping. Zener diodes Z1, Z2 connect back to back in series betweenpoints A and B so that one will conduct and dissipate energy by heatingif the voltage at point X is driven positive, and the other will conductand dissipate energy if the voltage at point X is driven negative. Onediode operates in a rectifier mode when the other device in a Zenermode.

In practice the Zener diodes Z1, Z2 do not switch well at high speed.This condition may be compensated for by substituting the configurationof FIG. 23 for Zener diodes D1, D2. FIG. 23 includes Zener diodes Z1, Z2each placed back to back in series with respective conventional diodesDZ1, DZ2. The Zener/conventional diode series connections are thenplaced in parallel. In this configuration, Zeners diodes Z1, Z2 need notoperate in a rectifying mode.

A further consideration is that Zener diodes are not currently availablein particularly high power ratings. Presently the maximum power ratingfor a Zener diode is approximately 70W. Further, Zener diodes which dohave a relatively high power rating are typically expensive.Transistors, however, are relatively inexpensive and readily availablein very high power ratings. One way to overcome the limitations ofZeners is to use an active Zener circuit such as shown in FIG. 24. InFIG. 24, the Zener diode ZA primarily functions to turn on a transistorTA which is configured for dissipating higher power levels,approximately 100 times that of Zener diode ZA. The power dissipation intransistor TA is a function of the gain of the active Zener circuit.

With reference to FIG. 24, when diode ZA is in a Zener mode, thefollowing equations apply:

V=V ₂ +V _(BE), where V _(BE)≈0.6 v

I=I ₂ +I _(Q), where I _(Q) ≈HFE×I ₂ and HFE 100 so that I _(Q) >>I ₂,and P _(Q) >>P ₂.

As can be seen from the equations above, the current through transistorTA is much greater than the current through Zener diode ZA, and thepower dissipated by transistor TA is much greater than the powerdissipated by the Zener diode ZA.

FIG. 25 depicts an alternate arrangement for setting a voltage referenceother than the negative and positive rails of the inverter. Inparticular, FIG. 25 shows a diode bridge comprising diodes DB1A, DB2A,DB1B, DB2B. A Zener ZB is connected across the halves of the diodebridge. Accordingly, whether for a negative wave or positive wave, Zenerdiode ZB enters Zener mode when the voltage exceeds the thresholdvoltage. FIG. 26 depicts a diode bridge arrangement similar to FIG. 25,but includes a transistor TA and Zener diode ZA arrangement similar toFIG. 24, thereby providing increased power dissipation.

The diode bridge circuits of FIGS. 24-26 provide several advantages.First, the design reduces cost because only one Zener diode must beused, rather than two. Second, because only one Zener diode is used,consistent clamping voltages may be obtained, rather than possiblyinconsistent clamping voltages obtained using a two Zener diodearrangement. Third, conventional diodes are much more easily matchedthan the Zener diodes.

FIG. 27 shows waveforms measured for an exemplary circuit implementationof a power supply having a protection circuit. Operating waveforms andpower levels were recorded for 300V DC input under matched andmismatched conditions. The load impedances matched at 50 ohms andmismatched using open circuit, short-circuit, and 12, 25, 50, 100 and200 ohms both inductive and capacitive reactive. With reference to FIG.27a-m, each figure includes four waveforms, labeled 1-4 in each figure.Waveform 1 indicates the drain voltage of the MOSFETs, such as theoutput input of inductor L1, at 200 volts per division. Waveform 2indicates the current through L1, at 10 amps per division. Waveform 3 isthe clamp voltage or voltage at the node between diodes D1, D2, atapproximately 200 volts per division. Waveform 4 is the clamping diodecurrent, at 10 amps per division. These conventions apply to each of theoutput waveforms of FIGS. 27 and 28. The selected values provide 12discreet points at infinite VSWR sufficient to ensure worst operatingconditions are found. The table below lists the key parameters:

DC RF Forward Power Peak FET Diode Current Power Dissipation CurrentCurrent Load (Amps) (Watts) (Watts) (Amps) (Amps) 50 ohms 1.71 465 48 104 Open Ckt. 0.109 138 33 10 0 Inductive 200 ohm 0.139 145 42 12 0 1000.162 157 49 13 0  50 0.226 176 68 14 10  25 0.240 155 72 14 18  120.242 149 73 13 23 Short Ckt. 0.204 202 61 10 24 Capacitive  12 ohm0.184 231 55 9 23  25 0.173 342 52 7 23  50 0.071 300 22 4 0 100 0.073190 22 7 0 200 0.088 150 26 9 0

As the load rotates from open circuit to short circuit inductively, thenback again capacitively, the FET currents are maintained inductive andare less than 40% higher than the 50 ohm value. DC current consumptionis only a one-sixth of the 50 ohm value. The clamping diodes D1, D2 canbe seen to conduct slightly with a 50ohm load, which could be eliminatedby slightly retuning the network. This, however, is not critical toeffective protection.

By way of contrast, FIG. 28 depicts output waveforms for a 375 KHz halfbridge inverter implemented without the clamp circuit. During thetesting, the test device was protected to avoid device destruction bymanually reducing the supply voltage. The table below lists the keyparameters. Protection now is accomplished by reducing the supplyvoltage.

RF Forward Power Peak FET DC Current Power Dissipation Current Load(Amps) (Watts) (Watts) (Amps) 50 ohms 1.86 514 44 10 Inductive 50 ohm0.25 241 75 15 25 0.41 424 124 18 12 0.36 @ 200 V 331 73 14 Short Ckt2.15 @ 42 V  752 90 14 Capacitive 12 ohm 0.46 @ 40 V  53 23 2.0 25 0.12@ 50 V  21 6 0.5

As the inductive load impedance is reduced, the FET currents becomelarger. If at 12 ohms the supply was maintained at 300V, forward powerwould have reached 750W, more than the 50 ohm value. At short circuit,750W is produced from only 42V, with L1 resonant with the rest of thenetwork. At 300V, forward RF power would be some 38 KW, DC power 4.6 KWand the peak transistor current 100A.

As the load swings capacitive and the impedance starts to rise, the FETssee a capacitive load. This condition can be more problematic than thehigh inductive currents seen before resonance because the FETs willsuffer high diode recovery loss even though the currents are stillmodest. Further there also is a risk of commutating dv/dt failure. Notein the last three graphs the scales have been changed for clarity.

FIG. 29 depicts a control circuit for a power generator. Control circuit20 includes a filter soft start rectifier 22 which receives an inputvoltage. Rectifier 22 may include a circuit breaker for overvoltageprotection. An auxiliary power sense unit (PSU) 24 generates a lowervoltage signal for powering control circuitry. A cooling fan 26 providescooling to the generator circuit.

The output from the filter soft start rectifier 22 is applied to anoptional DC switch 28 which controls the application of the DC voltageto a plurality of power amplifiers 30 a, 30 b, 30 c, 30 d. Four powersamplifiers 30 a-30 d are used in parallel in order to divide powerhandling across four amplifiers, rather than requiring one amplifier tohandle the entirety of the power. Alternatively, one or many poweramplifiers may carry out the function of power amplifiers 30 a-30 d. Adriver circuit 32 generates switching signals to control the switchingof each of the respective power amplifiers 30 a-30 d.

The output from power amplifiers 30 a-30 d is input to combining andisolating transformer 34 which combines each of the outputs from poweramplifiers 30 a-30 d into one signal. Combining circuit 34 may includean isolation transformer to isolate the power amplifiers from theoutput. Combining isolation transformer 34 outputs the combined signalto a filter and power sense circuit 36 which filters the power signalprior to generating the output. The power sense portion of the circuit36 provides a feedback signal to control phase modulator protectioncircuit 38.

Control phase modulator circuit 38 may be implemented using analog ordigital electronics. The circuit 38 outputs a control signal to each ofDC switch 28, driver 32, and front panel control 40. By varying thephase of switching of within each of the respective power amplifiers 30a-30 d, the output power may be correspondingly varied. Accordingly,control phase modulator circuit 38 varies the phase of the poweramplifier in accordance with input from the filter and power sensecircuit 36. Front panel control circuit 40 provides information to theoperator and also enables for variation of the desired phase andconsequent output power.

FIG. 30 depicts a control system where selected power supplies describedherein may be used in a system for controlling a plasma chamber. Controlsystem 50 includes a plasma chamber 52, such as may be used forfabricating integrated circuits. Plasma chamber 52 includes one or aplurality of gas inlets 54 and one or a plurality of gas outlets 56. Gasinlets 54 and outlets 56 enable the introduction and evacuation of gasfrom the interior of plasma chamber 52. The temperature within plasmachamber 52 may be controlled through a heat control signal 58 applied toplasma chamber 52. A plasma controller 60 receives inputs from theplasma chamber including a vacuum signal 62 which indicates the level ofvacuum in the chamber, a voltage signal 64, and a signal 66 indicatingthe ratio of flows between the inlet and outlet gases. As one skilled inthe art will recognize, other inputs/outputs may also bereceived/generated by plasma controller 60. Plasma controller 60determines a desired input power to be applied to plasma chamber througha voltage generator 68. Voltage generator 68 includes a microprocessor70, or other similar controller, which receives the input signal fromplasma controller 60. Microprocessor 70 generates control signals topower supply 72 which outputs a voltage signal at a desired frequencyand power rating. The voltage output from power supply 72 is input to amatching network 74 which matches impedances between power supply 72 andplasma chamber 52.

FIG. 31 depicts a circuit for a matching network 80, such as may beimplemented for matching network 70 of FIG. 30. Matching network 80desirably matches a 50 ohm input impedance with the output impedancesupplied by a load 82. Matching network 80 is configured in a pi filtertopology, including a first variable capacitor 84, a second variablecapacitor 86, and an inductor 88. Capacitors 84, 86 are implemented asvariable capacitors, so that the capacitance of the filter network maybe varied in order to properly match impedances between the 50 ohm inputand the load 82. A controller 88 receives a feedback signal which variesin accordance with the impedance matched and generates control signalswhich vary the capacitances of respective capacitors 84, 86. One skilledin the art that will recognize other matching network configurations mayalso be implemented, such as transformers or fixed networks.

While the invention has been described in its presently preferred form,it is to be understood that there are numerous applications andimplementations for the present invention. Accordingly, the invention iscapable of modification and changes without departing from the spirit ofthe invention as set forth in the appended claims.

What is claimed is:
 1. A power supply circuit for supplying alternatingpower to a load, comprising: a source of direct current (DC) voltage; ahalf-bridge inverter for receiving the DC input voltage and forgenerating an alternating current (AC) output signal; a first harmonicfilter at the output of the inverter, the first harmonic filterfiltering out predetermined harmonic components of the AC signal togenerate a filtered AC signal; and an output circuit at the output ofthe first harmonic filter for receiving the filtered AC signal andfeeding the filtered AC signal to a load, wherein the output circuitincludes first and second rectifiers connected relative to a point inthe output circuit such that if the inverter attempts to drive the pointto a voltage which exceeds one of a predetermined first and secondvoltage, a respective one of the first and second rectifiers conducts tocause at least one of voltage and current to return to the source of DCvoltage.
 2. The apparatus of claim 1 wherein the first harmonic filterincludes an inductor and a capacitor in series, and the first harmonicfilter is placed in parallel with one of the switches of thehalf-bridge.
 3. The apparatus of claim 1 wherein the first harmonicfilter includes an inductor and a capacitor, and the inductor is placedbetween an output of the switches of the half-bridge and aninterconnection between the first and second rectifiers, and thecapacitor further comprises a combined capacitance of a pair ofcapacitors each in parallel with the respective first and secondrectifier.
 4. The apparatus of claim 1 wherein the first and secondrectifiers each further comprise a pair of diodes in series, and thefirst harmonic filter includes an inductor and a capacitor, and theinductor is placed between an output of the switches and aninterconnection between the first and second diodes, and the capacitorfurther comprises a combined capacitance of a plurality of capacitors,where each capacitor corresponds to one of each respective pair ofdiodes, each in parallel with a corresponding, respective diode.
 5. Theapparatus of claim 1 further comprising: a pair of capacitors placed inseries between the respective voltage rails of the DC voltage source;the inverter comprising a pair of switches placed in series between therespective voltage rails of the DC voltage source; and an inductorplaced between an interconnection of the capacitors and aninterconnection of the switches.
 6. The apparatus of claim 5 furthercomprising a pair of diodes, each diode being in parallel with arespective capacitor.
 7. The apparatus of claim 5 wherein the switcheseach further comprise a pair of switches in series, and furthercomprising a capacitor in parallel with each switch.
 8. A power supplycircuit for supplying alternating power to a load, comprising: a sourceof direct current (DC) voltage; a full-bridge inverter for receiving theDC input voltage and for generating an alternating current (AC) outputsignal, the full bridge inverter comprising a pair of half bridges; afirst harmonic filter at the output of each respective half bridge, theharmonic filter filtering out predetermined harmonic components of theAC signal to generate a filtered AC signal; and an output circuit at thecombined output of the first harmonic filters, the output circuitreceiving the filtered AC signal and feeding the filtered AC signal to aload, wherein the output circuit includes first and second rectifiersconnected relative to a point in the output circuit such that if theinverter attempts to drive the point to a voltage which exceeds one of apredetermined first and second voltage, a respective one of the firstand second rectifiers conducts to cause at least one of voltage andcurrent to return to the source of DC voltage.
 9. The apparatus of claim8 further comprising a second harmonic filter at the combined output ofthe first harmonic filters, the second harmonic filter removing harmoniccomponents from the filtered AC signal to generate an output signal. 10.The apparatus of claim 9 further comprising a blocking capacitor at theoutput of the second harmonic filter for removing DC components from theoutput of the second harmonic filter.
 11. The apparatus of claim 9wherein the first harmonic filter includes an inductor and a capacitorin series, and the first harmonic filter is placed in parallel with oneof the switches of the half-bridge.
 12. The apparatus of claim 10wherein the second harmonic filter includes an inductor and a capacitorin series, and the second harmonic filter is placed in parallel with oneof the switches of the half-bridge.
 13. The apparatus of claim 9 whereinthe first harmonic filter includes an inductor and a capacitor, and theinductor is placed between an output of the switches and aninterconnection between the first and second rectifiers, and thecapacitor further comprises a combined capacitance of a pair ofcapacitors each in parallel with the respective first and secondrectifier.
 14. The apparatus of claim 13 wherein the second harmonicfilter includes an inductor and a capacitor, and the inductor is placedbetween an output of the switches and an interconnection between thefirst and second rectifiers, and the capacitor further comprises acombined capacitance of a pair of capacitors each in parallel with therespective second and second rectifier.
 15. The apparatus of claim 9further comprising: a pair of capacitors placed in series between therespective voltage rails of the DC voltage source; the invertercomprising a pair of switches placed in series between the respectivevoltage rails of the DC voltage source; and an inductor placed betweenan interconnection of the capacitors and an interconnection of theswitches.
 16. The apparatus of claim 15 further comprising a pair ofdiodes, each diode being in parallel with a respective capacitor. 17.The apparatus of claim 8 further comprising a signal generatorgenerating switching signal to each half of the inverter.
 18. Theapparatus of claim 17 wherein the signal generator varies a relativephase of operation between the first and second bridge halves.
 19. Theapparatus of claim 8 wherein at least one of the voltage and current isfed back into the inverter.
 20. A power supply circuit for supplyingalternating power to a load, comprising: a source of direct current (DC)voltage; a pair of single ended inverters for receiving the DC inputvoltage and for generating an alternating current (AC) output signal,the single ended inverters formed in a full bridge configuration; afirst harmonic filter at the output of each respective half bridge, theharmonic filter filtering out predetermined harmonic components of theAC signal to generate a filtered AC signal; and an output circuit at thecombined output of the first harmonic filters, the output circuitreceiving the filtered AC signal and feeding the filtered AC signal to aload, wherein the output circuit includes first and second rectifiersconnected relative to a point in the output circuit such that if theinverter attempts to drive the point to a voltage which exceeds one of apredetermined first or second voltage, a respective one of the first andsecond rectifiers conducts to cause at least one of voltage and currentto return to the source of DC voltage.
 21. The apparatus of claim 20wherein each single ended inverter comprises: a switch connected to afirst rail of the DC voltage source; a tank circuit connected betweenthe first and a second voltage rail of the DC voltage source, whereinoperating the switch energizes the tank circuit.
 22. The apparatus ofclaim 21 wherein the tank circuit further comprises: an inductorconnected between the switch and the second rail of the DC voltagesource; and a capacitor in parallel with the switch.
 23. The apparatusof claim 21 further comprising a blocking capacitor between the switchand the first harmonic filter.
 24. The apparatus of claim 20 furthercomprising a second harmonic filter at the combined output of the firstharmonic filters, the second harmonic filter removing harmoniccomponents from the filtered AC signal to generate an output signal. 25.The apparatus of claim 24 further comprising a blocking capacitor at theoutput of the second harmonic filter for removing DC components from theoutput of the second harmonic filter.
 26. The apparatus of claim 25wherein the first harmonic filter includes an inductor and a capacitorin series, and the first harmonic filter is placed in parallel with oneof the switches of the half-bridge.
 27. The apparatus of claim 26wherein the second harmonic filter includes an inductor and a capacitorin series, and the second harmonic filter is placed in parallel with oneof the switches of the half-bridge.
 28. The apparatus of claim 25wherein the first harmonic filter includes an inductor and a capacitor,and the inductor is placed between an output of the switches and aninterconnection between the first and second rectifiers, and thecapacitor further comprises a combined capacitance of a pair ofcapacitors each in parallel with the respective first and secondrectifier.
 29. The apparatus of claim 28 wherein the second harmonicfilter includes an inductor and a capacitor, and the inductor is placedbetween an output of the switches and an interconnection between thesecond and second rectifiers, and the capacitor further comprises acombined capacitance of a pair of capacitors each in parallel with therespective second and second rectifier.
 30. The apparatus of claim 20further comprising: a pair of capacitors placed in series between therespective voltage rails of the DC voltage source; the invertercomprising a pair of switches placed in series between the respectivevoltage rails of the DC voltage source; and an inductor placed betweenan interconnection of the capacitors and an interconnection of theswitches.
 31. The apparatus of claim 29 further comprising a pair ofdiodes, each diode being in parallel with a respective capacitor. 32.The apparatus of claim 21 further comprising a signal generatorgenerating switching signal to each half of the inverter.
 33. Theapparatus of claim 32 wherein the signal generator varies a relativephase of operation between the first and second bridge halves.
 34. Theapparatus of claim 21 wherein the voltage and/or current is fed backinto the inverter.
 35. A power supply circuit for supplying alternatingpower to a load, comprising: a source of direct current (DC) voltage; afirst plurality of single ended inverters arranged in series betweenfirst and second rails of the DC voltage source, the first plurality ofsingle ended inverters forming a first half of a bridge configuration,the first half of the bridge having a first combined output; a secondplurality of single ended inverters arranged in series between first andsecond rails of the DC voltage source, the second plurality of singleended inverters forming a second half of a bridge configuration, thesecond half of the bridge having a second combined output; a firstharmonic filter at the output of each respective bridge half, theharmonic filter filtering out predetermined harmonic components of theAC signal to generate a filtered AC signal; and an output circuit at thecombined output of the first harmonic filters, the output circuitreceiving the filtered AC signal and feeding the filtered AC signal to aload, wherein the output circuit includes first and second rectifiersconnected relative to a point in the output circuit such that if theinverter attempts to drive the point to a voltage which exceeds one of apredetermined first and second voltage, a respective one of the firstand second rectifiers conducts to cause at least one of voltage andcurrent to the source of DC voltage.
 36. The apparatus of claim 35wherein at least one single ended inverter comprises: a switch connectedto a first local voltage rail; and a tank circuit connected between asecond local voltage and the switch, wherein the switch energizes thetank circuit.
 37. The apparatus of claim 36 wherein the tank circuitfurther comprises: an inductor connected between the switch and thesecond local voltage rail; and a capacitor in parallel with the switch.38. The apparatus of claim 36 wherein the local voltage rail for a firstbridge half has a corresponding local voltage rail for a second bridgehalf, wherein the local voltage rail for a first bride half and thecorresponding local voltage rail of the second bridge half areinterconnected.
 39. The apparatus of claim 36 further comprising ablocking capacitor between each switch and the first harmonic filter.40. The apparatus of claim 36 further comprising a second harmonicfilter at the combined output of the first harmonic filters, the secondharmonic filter removing harmonic components from the filtered AC signalto generate an output signal.
 41. A power supply circuit for supplyingalternating power to a load, comprising: a source of direct current (DC)voltage; a full-bridge inverter for receiving the DC input voltage andfor generating an alternating current (AC) output signal, thefull-bridge inverter comprising a pair of half-bridges; a harmonicfilter at the output of the inverter, the harmonic filter filtering outpredetermined harmonic components of the AC signal to generate afiltered AC signal; and an output circuit at the output of the harmonicfilter for receiving the filtered AC signal and feeding the filtered ACsignal to a load, wherein the output circuit includes at least onerectifier connected relative to a point in the output circuit such thatif the inverter attempts to drive the point to a voltage which exceedsone of a predetermined first and second voltage, the at least onerectifier conducts to cause at least one of voltage and current todissipate, wherein the predetermined first and second voltages are otherthan the voltages of respective positive and negative rails of the DCvoltage source.
 42. The apparatus of claim 41 wherein the at least onerectifier is a Zener diode.
 43. The apparatus of claim 41 wherein the atleast one rectifier comprises a pair of Zener diodes arranged back toback, and the breakdown voltages of each Zener diode determines thepredetermined first and second voltages.
 44. The apparatus of claim 42further comprising a second harmonic filter at the output of the firstharmonic filter, the second harmonic filter removing harmonic componentsfrom the filtered AC signal to generate an output signal.
 45. Theapparatus of claim 43 wherein the at least one Zener diode is insertedbetween a common voltage reference and the output of the first harmonicfilter.
 46. The apparatus of claim 42 wherein the at least one rectifieractuates a switch to enable the switch to conduct current and dissipatepower.
 47. The apparatus of claim 42 wherein the at least one rectifierinterconnects two halves of a diode bridge.
 48. A control system for apower generator, comprising: a circuit for receiving an AC signal andconverting the AC signal to a DC voltage signal; a power amplifierincluding: a full bridge inverter for receiving the DC voltage signaland for generating an AC output signal, the full bridge having first andsecond halves, and an output circuit, the output circuit receiving thefiltered AC signal and feeding the filtered AC signal to a load, whereinthe output circuit includes first and second rectifiers connectedrelative to a point in the output circuit such that if the inverterattempts to drive the point to a voltage which exceeds one of apredetermined first and second voltage, a respective one of the firstand second rectifiers conducts to cause at least one of voltage andcurrent to return to the inverter; and an output sense circuit fordetermining a power of the output signal the output sense circuitgenerating a sense signal; and a phase modulator for varying therelative phases of the full bridge to vary the output power inaccordance with the sense signal.
 49. The apparatus of claim 47 whereinthe power amplifier comprises a plurality of power amplifiers arrangedin parallel and the apparatus further comprises a combiner for combiningthe output signal of each of the plurality of inverters.
 50. A plasmacontrol system comprising: a plasma chamber excited by a radio frequency(RF) signal; a plasma controller for measuring operating conditions ofthe plasma chamber and generating control signals for varying conditionswithin the plasma chamber; and a RF generator for generating an RFsignal to the plasma chamber, the RF generator including: a RFcontroller, the RF controller receiving the control signal from theplasma controller an generating a power supply control signal, and apower supply for receiving the power supply control signal andgenerating a RF signal in accordance with the power supply controlsignal, wherein the power supply includes a protection circuit includingfirst and second rectifiers connected relative to a predetermined pointsuch that such that if the power supply attempts to drive thepredetermined point to a voltage which exceeds one of a predeterminedfirst and second voltage, a respective one of a first and secondrectifiers conducts.
 51. The apparatus of claim 50 wherein the powersupply further comprises: a source of direct current (DC) voltage; ahalf-bridge inverter for receiving the DC input voltage and forgenerating an alternating current (AC) output signal; a harmonic filterat the output of the inverter, the harmonic filter filtering outpredetermined harmonic components of the AC signal to generate afiltered AC signal; and an output circuit at the output of the harmonicfilter for receiving the filtered AC signal and feeding the filtered ACsignal to a load, wherein the output circuit includes the first andsecond rectifiers connected relative to the point in the output circuit.52. The apparatus of claim 50 wherein the power supply furthercomprises: a source of direct current (DC) voltage; a full-bridgeinverter for receiving the DC input voltage and for generating analternating current (AC) output signal, the full bridge invertercomprising a pair of half bridges; a first harmonic filter at the outputof each respective half bridge, the harmonic filter filtering outpredetermined harmonic components of the AC signal to generate afiltered AC signal; and an output circuit at the combined output of thefirst harmonic filters, the output circuit receiving the filtered ACsignal and feeding the filtered AC signal to a load, wherein the outputcircuit includes the first and second rectifiers connected relative tothe point in the output circuit.
 53. A power supply circuit forsupplying alternating power to a load, comprising: a source of directcurrent (DC) voltage; an inverter for receiving the DC input voltage andfor generating an alternating current (AC) output signal for input to aload; an output circuit at the output of the inverter; and a returncircuit connected to a point in the output circuit such that if thevoltage at the point exceeds one of a predetermined first and secondvoltage, the return circuit conducts to cause at least one of voltageand current to return to the source of DC voltage.
 54. The apparatus ofclaim 53 wherein the output circuit further comprises a harmonic filter.55. The apparatus of claim 53 wherein the output circuit furthercomprises a harmonic filter including an inductor and a capacitor. 56.The apparatus of claim 53 wherein the return circuit comprises first andsecond rectifiers.
 57. The apparatus of claim 53 wherein the invertercomprises a half bridge inverter.
 58. The apparatus of claim 53 whereinthe inverter comprises a full bridge inverter having two halves, and thehalves are placed in one of series and parallel with the load.
 59. Theapparatus of claim 53 wherein the return circuit returns at least one ofvoltage and current to return to the inverter.
 60. A power supplycircuit for supplying alternating power to a load, comprising: a sourceof direct current (DC) voltage; an inverter for receiving the DC inputvoltage and for generating an alternating current (AC) output signal forinput to a load; an output circuit at the output of the inverter; and adissipation circuit connected to a point in the output circuit such thatif the voltage at the point exceeds one of a predetermined first andsecond voltage, the dissipation circuit conducts to cause at least oneof voltage and current to dissipate.
 61. The apparatus of claim 60 thedissipation circuit comprises at least one Zener diode.
 62. Theapparatus of claim 60 wherein the dissipation circuit comprises a pairof Zener diodes arranged back to back, and the breakdown voltages ofeach Zener diode determines the predetermined first and second voltages.